RPT5032A
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PLUTO+ ™ ULTRA STABLE SMD TCXO RPT5032A The RPT5032A encompasses Rakon's new patented Pluto+ ASIC. Pluto+ advances on the world famous, Pluto ASIC technology by delivering exceptional phase noise and jitter performance, and enhanced frequency versus temperature stability. The single chip oscillator with its analogue compensation circuit is capable of sub 0.1ppm frequency stability over an extended temperature range and RMS phase jitter down to 0.13ps for IEEE1588 and SyncE applications. Its unique tilt control ensures lifetime specification compliance, unlike other TCXOs available. Best in class frequency versus temperature Time and frequency reference RMS phase jitter down to 0.13ps Phase noise < ‐160dBc/Hz noise floor Voltage control and T‐sense options available Hi‐Rel / Defense Standard Specifications Parameter Nominal frequency Test Condition / Description Frequency calibration Reflow shift Pre to post reflow ΔF (measured ≥ 60 minutes after reflow) Reference to (Fmax + Fmin)/2. The best available stability depends on the nominal frequency and Operating temperature range Frequency stability over temperature selected operating temperature range Supply voltage stability Load sensitivity ±5% variation Reference to frequency at nominal VCC  HCMOS, ACMOS: ±5pF variation,  Clipped sine wave / Sine wave: ±10% variation reference to frequency at nominal load ppm/year ppm/year Long term stability (aging) ≤26MHz >26MHz Acceleration Stability Start‐up time Supply voltage, VCC Current (C/Sine) Current (Sine) Current (HCMOS) Current (ACMOS) Root Allan Variance (20MHz) Oscillator output options Tri‐State Control Input level low (pin 6) Input level high (pin 6) tau = 1.0s Clipped sine wave, sine wave, HCMOS (LVCMOS & LVTTL compatible as per JESD8C) and ACMOS Device disabled, output

PLUTO+ ™ ULTRA STABLE SMD TCXO SSB Phase Noise (Typical value at 25°C) SSB Phase Noise (dBc/Hz) Model Outline and Recommended Pad Layout Test Circuit