RPT5032A

Product catalog summary

Overview: The RPT5032A is a highly stable SMD TCXO featuring Rakon's patented Pluto+ ASIC technology. It offers exceptional phase noise and jitter performance, with enhanced frequency stability over temperature.

Specifications:

Nominal Frequency: 1.25–52 MHz, with standard frequencies including 10.0, 12.8, 16.384, 19.2, 19.44, 20.0, 25.0, 26.0, 30.72, 38.88, and 40 MHz.
Frequency Calibration: ±1 ppm initial accuracy at 25 ± 1°C.
Reflow Shift: ±0.5 ppm measured ≥ 60 minutes after reflow.
Operating Temperature Range: -55 to 105°C.
Frequency Stability: ±0.05 to ±2.5 ppm over temperature, depending on nominal frequency and temperature range.
Supply Voltage Stability: ±0.025 ppm with ±5% variation.
Load Sensitivity: ±0.05 ppm for HCMOS, ACMOS, and ±10% variation for clipped sine wave/sine wave.
Long Term Stability (Aging): ≤26MHz: ±1 ppm/year, >26MHz: ±2 ppm/year.
Acceleration Stability: <2 ppb/g across 3-axes, 30-1500Hz.
Start-up Time: 5–15 ms to 90% amplitude.
Supply Voltage (VCC): 2.5 to 5.7 V with standard values of 3.0, 3.3, and 5.0V.
Control Voltage (Vc): 0.5 to 2.5 V.
Frequency Tuning: ≤26MHz: ±5 ppm, >26MHz: ±7 ppm.
Root Allan Variance (20MHz): 5 x 10^-11 at tau = 1.0s.
Oscillator Output Options: Clipped sine wave, sine wave, HCMOS, and ACMOS.
Tri-State Control: Device disabled at 0.6VCC, enabled at 0.2VCC.

Features:

Best in class frequency versus temperature stability.
RMS phase jitter down to 0.13ps.
Phase noise < -160dBc/Hz noise floor.
Voltage control and T-sense options available.

Applications: Suitable for time and frequency reference, positioning, test and measurement, telecommunications, and high-reliability/defense sectors.

Additional Information: The document includes typical SSB phase noise values at 25°C, model outline, recommended pad layout, and test circuit details.

Catalog excerpts

PLUTO+ ™ ULTRA STABLE SMD TCXO RPT5032A The RPT5032A encompasses Rakon's new patented Pluto+ ASIC. Pluto+ advances on the world famous, Pluto ASIC technology by delivering exceptional phase noise and jitter performance, and enhanced frequency versus temperature stability. The single chip oscillator with its analogue compensation circuit is capable of sub 0.1ppm frequency stability over an extended temperature range and RMS phase jitter down to 0.13ps for IEEE1588 and SyncE applications. Its unique tilt control ensures lifetime specification compliance, unlike other TCXOs available. Best in class frequency versus temperature Time and frequency reference RMS phase jitter down to 0.13ps Phase noise < ‐160dBc/Hz noise floor Voltage control and T‐sense options available Hi‐Rel / Defense Standard Specifications Parameter Nominal frequency Test Condition / Description Frequency calibration Reflow shift Pre to post reflow ΔF (measured ≥ 60 minutes after reflow) Reference to (Fmax + Fmin)/2. The best available stability depends on the nominal frequency and Operating temperature range Frequency stability over temperature selected operating temperature range Supply voltage stability Load sensitivity ±5% variation Reference to frequency at nominal VCC  HCMOS, ACMOS: ±5pF variation,  Clipped sine wave / Sine wave: ±10% variation reference to frequency at nominal load ppm/year ppm/year Long term stability (aging) ≤26MHz >26MHz Acceleration Stability Start‐up time Supply voltage, VCC Current (C/Sine) Current (Sine) Current (HCMOS) Current (ACMOS) Root Allan Variance (20MHz) Oscillator output options Tri‐State Control Input level low (pin 6) Input level high (pin 6) tau = 1.0s Clipped sine wave, sine wave, HCMOS (LVCMOS & LVTTL compatible as per JESD8C) and ACMOS Device disabled, output

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PLUTO+ ™ ULTRA STABLE SMD TCXO SSB Phase Noise (Typical value at 25°C) SSB Phase Noise (dBc/Hz) Model Outline and Recommended Pad Layout Test Circuit

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RPT5032A

RPT5032A

Catalog excerpts

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