DVFL2800S
1 / 30Pagine

DVFL2800S Series HIGH RELIABILITY HYBRID DC-DC CONVERTERS DESCRIPTION The DVFL series of high-reliability DC-DC converters provide decades of successful critical mission support. Operable over the full military (-55 °C to +125 °C) temperature range with no power derating, the DVFL series unique input, and output filters dramatically reduce input and output noise performance. While operating at a nominal fixed frequency of 450 kHz, these regulated, isolated units utilize a high-speed magnetic feedback design and well-controlled under-voltage lockout circuitry to eliminate slow start-up problems. These converters are designed and manufactured in a facility qualified to ISO9001 and certified to MIL-PRF-38534 and MIL-STD-883. This product may incorporate one or more of the following U.S. patents: 5,784,266 5,790,389 5,963,438 5,999,433 6,005,780 6,084,792 6,118,673 FEATURES • High Reliability • Parallel Up to 5 Units With Current Sharing • Output Voltage Trim Up +10% or Down -20% • Wide Input Voltage Range: 16 to 40 Volts per MIL-STD-704 • Up to 120 Watts Output Power • Fault Tolerant Magnetic Feedback Circuit • NO Use of Optoisolators • Undervoltage Lockout • Indefinite Short Circuit Protection • Current Limit Protection • Industry Standard Pinout • Input Transient Voltage: 50 Volts for 1 second • Precision Seam Welded Hermetic Package • High Power Density: > 80 W/in3 • Custom Versions Available • Additional Environmental Screening Available • Meets MIL-STD-461 EMC Requirements when used with VPT’s EMI Filters. • MIL-PRF-38534 Element Evaluated Components • Space Applications should consider VPT’s "S” Series of Radiation Tolerant Power Conversion Devices. Contact VPT for details. Sales Information: Phone: (425) 353-3010 Fax: (425) 353-4030 E-mail: vptsales@vptpower.com

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified. 5. Correction factor of 0.12 added to ceramic capacitors.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 3. Derate linearly to 0 at 135°C. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified. 5. Correction factor of 0.12 added to ceramic capacitors.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 3. Derate linearly to 0 at 135°C. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified. 5. Correction factor of 0.12 added to ceramic capacitors.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 3. Derate linearly to 0 at 135°C. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified. 5. Correction factor of 0.12 added to ceramic capacitors.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 3. Derate linearly to 0 at 135°C. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified. 5. Correction factor of 0.12 added to ceramic capacitors.

1. Dependent on output voltage. 2. Time for output voltage to settle within 1 % of its nominal value. 3. Derate linearly to 0 at 135°C. 4. Verified by initial electrical design verification. Post design verification, parameter shall be guaranteed to the limits specified.

DVFL2800S Series BLOCK DIAGRAM PIN 1 UNDER VOLTAGE SHUTDOWN VOLTAGE AND CURRENT AMPLIFIERS PRIMARY HOUSEKEEPING SUPPLY SECO NDARY HOUSEKEEPING SUPPLY

DVFL2800S Series INHIBIT DRIVE CONNECTION DIAGRAM 28V IN 1 30K OPTOISOLATOR OPTIONAL CAPACITOR Figure 4 – Isolated Inhibit Drive and Internal Equivalent Circuit (Shown with optional capacitor for turn-on delay) EMI FILTER HOOKUP DIAGRAM DVME28 EMI FILTER 1 Figure 5 – Converter with EMI Filter

DVFL2800S Series PARALLEL CONNECTION DIAGRAMS CASE DVFL2800S DC-DC CONVERTER 1 CASE DVFL2800S DC-DC CONVERTER 1 Figure 6 – Current Sharing Parallel Connection for Multiple Converters

The output voltage can be trimmed down by connecting a resistor between the TRIM pin (PIN 3) and the +V OUT pin (PIN 7), or can be trimmed up by connecting a resistor between the TRIM pin (PIN 3) and the OUT COM pin (PIN 8). The maximum trim range is +10% up and -20% down. The appropriate resistor values versus the output voltage are given in the trim table below. (continued on next page)

DVFL2800S Series EFFICIENCY PERFORMANCE CURVES (TCASE = 25°C, Full Load, Unless Otherwise Specified) VIN = 16V Efficiency (%) vs. Output Power (W) Efficiency (%) vs. Output Power (W) Efficiency (%) vs. Output Power (W) Efficiency (%) vs. Output Power (W)